In asynchronous transmission, data is coded into a series of pulses, including a start bit, and including a stop bit or a guard band. The start bit is sent by a sending unit to inform a receiving unit that a character is to be sent. The character is then sent, followed by the stop bit or guard band, designating that the transfer of that character is complete. Modes of asynchronous communication are frequently defined in standards that are established by standards setting bodies, such as the American National Standards Institute (ANSI), the International Telecommunications Union (ITU) and the International Organization for Standardization (ISO).
Asynchronous communication is frequently used to transfer data to and from plug-in units, such as modems, memory cards, and the like, that are plugged into host units, such as digital cameras, personal computers, and the like. An interface controller in the host unit manages the asynchronous data communication between the plug-in unit and the host unit. An exemplary asynchronous communication standard is the ISO7816 standard, adopted by the ISO. Plug-in units communicating with an interface controller in a manner that complies with the ISO7816 standard are frequently referred to as Smart Cards, or Integrated Circuit Cards.
FIG. 1 shows a typical Smart Card interface arrangement. A Smart Card unit 10 is electrically connected to a host unit 14 by way of an interface controller 12 in the host unit 14 that manages the transfer of data between the Smart Card unit 10 and the host unit 14. The transfer of data between the host unit 14 and the interface controller 12 is shown by way of example in FIG. 1 as being by way of a PCI bus 16 in the host unit 14. Numerous other means for communicating data between the interface controller and the host unit are possible, including EISA bus, universal serial bus (USB), and so on. The Smart Card connection to the host unit 14 is by way of a two-way serial line 11, which is split in the host unit 14 into a transmitting line 26 and a receiving line 30, using well known techniques. The rate of data exchange between the Smart Card unit 10 and the interface controller 12 is controlled by an interface clock, which can be at one of five different clock frequencies, 4 MHz, 6 MHz, 8 MHz, 12 MHz and 20 MHz.
The interface unit 12 includes a Smart Card interface subunit 18 and a PCI interface subunit 20. The Smart Card interface subunit 18 includes a Smart Card block 22 and a parity checker block 24. The Smart Card block 22 receives the signals transmitted on line 26 by the Smart Card unit 10, recovers the data in those signals, and then sends that data on line 27 to the PCI interface subunit where it is placed on the PCI bus 16 according to the well-known PCI standard protocol, for transmission to other parts (not shown) of the host unit 14. The parity checker block 24 monitors the data on line 26 to detect whether a parity error exists in a character of data. If such a parity error is so detected, the parity checker block 24 asserts a signal on line 28, which causes a gate 29 to block the Smart Card block 22 from receiving the error, and sends a signal on line 30 to the Smart Card unit 10 notifying it of the error, which prompts an attempted re-send of the affected character from the Smart Card unit 10.
When parity errors exist, it is frequently because of errors made in the coding of the data in the Smart Card unit 10. However, sometimes parity errors are detected in the parity checker block 24 because of the occurrence of glitches occurring on the signals sent from the Smart Card unit 10. This problem is not limited to asynchronous data communicated according to the ISO7816 standard, but is a problem with respect to asynchronous data communication generally. Further, it is not limited to systems in which errors are determined by parity checking; rather, it applies to such systems in which errors in the data can occur because of glitches. It would be desirable to be able to be able to successfully detect data in asynchronous communication, even if glitches are present. It would also be desirable to avoid the time expenditure involved in error detecting and signaling, and re-send of data in systems wherein an error detecting and data re-send protocol is provided.